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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd442002-x 2m-bit cmos static ram 128k-word by 16-bit extended temperature operation data sheet document no. m14670ej7v 1 ds00 (7th edition) date published ju l y 200 4 ns cp (k) printed in japan the mark shows major revised points. 2000 description the pd442002-x is a high speed, low power, 2,097,152 bits (131,072 words by 16 bits) cmos static ram. the pd442002-x is packed in 48-pin tape fbga. features ? 131,072 words by 16 bits organization ? fast access time : 70, 85, 100 ns (max.) ? byte data control : /lb (i/o1 to i/o8), /ub (i/o9 to i/o16) ? low voltage operation : v cc = 2.7 to 3.6 v (-bb70x) v cc = 2.2 to 3.6 v (-bc70x) v cc = 1.8 to 2.2 v (-dd85x, -dd10x) ? low v cc data retention : 1.0 v (min.) ? operating ambient temperature : t a = ?25 to +85 c ? output enable input for easy application pd442002 access time operating supply operating ambient supply current ns (max.) voltage temperature at operating at standby at data retention v c ma (max.) a (max.) a (max.) -bb70x 70 2.7 to 3.6 ? 25 to +85 30 4 2 -bc70x 70 2.2 to 3.6 -dd85x, -dd10x 85, 100 1.8 to 2.2 15 3
data sheet m14670ej7v 1 ds 2 pd442002-x ordering information part number package access time operating operating ns (max.) supply voltage temperature v c pd442002f9-bb70x-bc2-a note 48-pin tape fbga (8 6) 70 2.7 to 3.6 ? 25 to +85 pd442002f9-bc70x-bc2-a note 70 2.2 to 3.6 pd442002f9-dd85x-bc2-a note 85 1.8 to 2.2 pd442002f9-dd10x-bc2-a note 100 note lead-free product marking image part number marking (xx) pd442002f9-bb70x-bc2-a b2 pd442002f9-bc70x-bc2-a c2 pd442002f9-dd85x-bc2-a d3 pd442002f9-dd10x-bc2-a d4 index mark lot no. j s2m0-xx
data sheet m14670ej7v 1 ds 3 pd442002-x pin configuration /xxx indicates active low signal. 48-pin tape fbga (8 6) a b c d e f g h 123456 bottom view 654321 top view 1 2 3 4 5 6 6 5 4 3 2 1 a /lb /oe a0 a1 a2 nc a nc a2 a1 a0 /oe /lb b i/o9 /ub a3 a4 /cs i/o1 b i/o1 /cs a4 a3 /ub i/o9 c i/o10 i/o11 a5 a6 i/o2 i/o3 c i/o3 i/o2 a6 a5 i/o11 i/o10 d gnd i/o12 nc a7 i/o4 v cc d v cc i/o4 a7 nc i/o12 gnd e v cc i/o13 nc a16 i/o5 gnd e gnd i/o5 a16 nc i/o13 v cc f i/o15 i/o14 a14 a15 i/o6 i/o7 f i/o7 i/o6 a15 a14 i/o14 i/o15 g i/o16 nc a12 a13 /we i/o8 g i/o8 /we a13 a12 nc i/o16 h nc a8 a9 a10 a11 nc h nc a11 a10 a9 a8 nc a0 to a16 : address inputs i/o1 to i/o16 : data inputs / outputs /cs : chip select /we : write enable /oe : output enable /lb, /ub : byte data select v cc : power supply gnd : ground nc : no connection remark refer to package drawing for the index mark.
data sheet m14670ej7v 1 ds 4 pd442002-x block diagram address buffer address buffer row decoder memory cell array 2,097,152 bits input data controller a0 a16 i/o9 to i/o16 column decoder /cs /we /oe /ub /lb output data controller i/o1 to i/o8 v cc gnd sense amplifier / switching circuit
data sheet m14670ej7v 1 ds 5 pd442002-x truth table /cs /oe /we /lb /ub mode i/o supply current i/o1 to i/o8 i/o9 to i/o16 h not selected high-z high-z i sb h h not selected high-z high-z l h h l output disable high-z high-z i cca l output disable high-z high-z l h l l word read d out d out l h lower byte read d out high-z h l upper byte read high-z d out l l l word write d in d in l h lower byte write d in high-z h l upper byte write high-z d in remark : v ih or v il
data sheet m14670ej7v 1 ds 6 pd442002-x electrical specifications absolute maximum ratings parameter symbol condition rating unit -bb70x, -bc70x -dd85x, -dd10x supply voltage v cc ?0.5 note to +4.0 ?0.5 note to +2.7 v input / output voltage v t ?0.5 note to v cc +0.4 (4.0 v max.) ?0.5 note to v cc +0.4 (2.7 v max.) v operating ambient temperature t a ?25 to +85 ?25 to +85 c storage temperature t stg ?55 to +125 ?55 to +125 c note ?3.0 v (min.) (pulse width : 30 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition -bb70x -bc70x -dd85x, -dd10x unit min. max. min. max. min. max. supply voltage v cc 2.7 3.6 2.2 3.6 1.8 2.2 v high level input voltage v ih 2.7 v v cc 3.6 v 2.4 v cc +0.4 2.4 v cc +0.4 ? ? v 2.2 v v cc < 2.7 v ? ? 2.0 v cc +0.3 ? ? 1.8 v v cc < 2.2 v ? ? ? ? 1.6 v cc +0.2 low level input voltage v il ?0.3 note +0.5 ?0.3 note +0.4 ?0.2 note +0.2 v operating ambient t a ?25 +85 ?25 +85 ?25 +85 c temperature note ?1.0 v (min.) (pulse width : 20 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 8 pf input / output capacitance c i/o v i/o = 0 v 10 pf remarks 1. v in : input voltage v i/o : input / output voltage 2. these parameters are not 100% tested.
data sheet m14670ej7v 1 ds 7 pd442002-x dc characteristics (recommended operating conditions unless otherwise noted) (1/2) parameter symbol test condition -bb70x unit min. typ. max. input leakage current i li v in = 0 v to v cc ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc , /cs = v ih or ?1.0 +1.0 a /we = v il or /oe = v ih operating supply current i cca1 /cs = v il , i i/o = 0 ma, minimum cycle time ? 30 ma i cca2 /cs = v il , i i/o = 0 ma, cycle time = ? 4 i cca3 /cs 0.2 v, cycle time = 1 s, i i/o = 0 ma, ? 4 v il 0.2 v, v ih v cc ? 0.2 v standby supply current i sb /cs = v ih or /lb = /ub = v ih ? 0.6 ma i sb1 /cs v cc ? 0.2 v 0.3 4 a i sb2 /lb = /ub v cc ? 0.2 v, /cs 0.2 v 0.3 4 high level output voltage v oh i oh = ?0.5 ma 2.4 v low level output voltage v ol i ol = 1.0 ma 0.4 v remark v in : input voltage v i/o : input / output voltage
data sheet m14670ej7v 1 ds 8 pd442002-x dc characteristics (recommended operating conditions unless otherwise noted) (2/2) parameter symbol test condition -bc70x -dd85x, -dd10x unit min. typ. max. min. typ. max. input leakage current i li v in = 0 v to v cc ?1.0 +1.0 ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc , /cs = v ih or ?1.0 +1.0 ?1.0 +1.0 a /we = v il or /oe = v ih operating supply current i cca1 /cs = v il , i i/o = 0 ma, ? 30 ? ? ma minimum cycle time v cc 2.7 v ? 25 ? ? v cc 2.2 v ? ? ? 15 i cca2 /cs = v il , i i/o = 0 ma, ? 4 ? ? cycle time = v cc 2.7 v ? 2 ? ? v cc 2.2 v ? ? ? 1 i cca3 /cs 0.2 v, cycle time = 1 s, ? 4 ? ? i i/o = 0 ma, v il 0.2 v, v cc 2.7 v ? 3 ? ? v ih v cc ? 0.2 v v cc 2.2 v ? ? ? 3 standby supply current i sb /cs = v ih or /lb = /ub = v ih ? 0.6 ? ? ma v cc 2.7 v ? 0.6 ? ? v cc 2.2 v ? ? ? 0.6 i sb1 /cs v cc ? 0.2 v 0.3 4 ? ? a v cc 2.7 v 0.25 3.5 ? ? v cc 2.2 v ? ? 0.2 3 i sb2 /lb = /ub v cc ? 0.2 v, 0.3 4 ? ? /cs 0.2 v v cc 2.7 v 0.25 3.5 ? ? v cc 2.2 v ? ? 0.2 3 high level output voltage v oh i oh = ?0.5 ma 2.4 ? v v cc 2.7 v 1.8 ? v cc 2.2 v ? 1.5 low level output voltage v ol i ol = 1.0 ma 0.4 ? v v cc 2.7 v 0.4 ? v cc 2.2 v ? 0.4 remark v in : input voltage v i/o : input / output voltage
data sheet m14670ej7v 1 ds 9 pd442002-x ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions input waveform (rise and fall time ? 5 ns) 0.1 v cc 0.9 v cc test points v cc /2 v cc /2 output waveform test points v cc /2 v cc /2 output load [ -bb70x ] 1ttl + 50 pf [ -bc70x, -dd85x, -dd10x ] 1ttl + 30 pf
data sheet m14670ej7v 1 ds 10 pd442002-x read cycle (1/2) parameter symbol v cc 2.7 v unit condition -bb70x min. max. read cycle time t rc 70 ns address access time t aa 70 ns note 1 /cs access time t acs 70 ns /oe to output valid t oe 35 ns /lb, /ub to output valid t ba 70 ns output hold from address change t oh 10 ns /cs to output in low impedance t lz 10 ns note 2 /oe to output in low impedance t olz 5 ns /lb, /ub to output in low impedance t blz 10 ns /cs to output in high impedance t hz 25 ns /oe to output in high impedance t ohz 25 ns /lb, /ub to output in high impedance t bhz 25 ns notes 1. the output load is 1ttl + 50 pf. 2. the output load is 1ttl + 5 pf. read cycle (2/2) parameter symbol v cc 2.2 v v cc 1.8 v unit condition -bc70x -dd85x -dd10x min. max. min. max. min. max. read cycle time t rc 70 85 100 ns address access time t aa 70 85 100 ns note 1 /cs access time t acs 70 85 100 ns /oe to output valid t oe 35 40 50 ns /lb, /ub to output valid t ba 70 85 100 ns output hold from address change t oh 10 10 10 ns /cs to output in low impedance t lz 10 10 10 ns note 2 /oe to output in low impedance t olz 5 5 5 ns /lb, /ub to output in low impedance t blz 10 10 10 ns /cs to output in high impedance t hz 25 30 35 ns /oe to output in high impedance t ohz 25 30 35 ns /lb, /ub to output in high impedance t bhz 25 30 35 ns notes 1. the output load is 1ttl + 30 pf. 2. the output load is 1ttl + 5 pf.
data sheet m14670ej7v 1 ds 11 pd442002-x read cycle timing chart t rc t oh t hz t blz t ba t lz t acs t bhz t aa high-z data out /lb, /ub (input) /cs (input) address (input) i/o (output) t olz t oe t ohz /oe (input) remark in read cycle, /we should be fixed to high level.
data sheet m14670ej7v 1 ds 12 pd442002-x write cycle (1/2) parameter symbol v cc 2.7 v unit condition -bb70x min. max. write cycle time t wc 70 ns /cs to end of write t cw 55 ns /lb, /ub to end of write t bw 55 ns address valid to end of write t aw 55 ns address setup time t as 0 ns write pulse width t wp 50 ns write recovery time t wr 0 ns data valid to end of write t dw 30 ns data hold time t dh 0 ns /we to output in high impedance t whz 25 ns note output active from end of write t ow 5 ns note the output load is 1ttl + 5 pf. write cycle (2/2) parameter symbol v cc 2.2 v v cc 1.8 v unit condition -bc70x -dd85x -dd10x min. max. min. max. min. max. write cycle time t wc 70 85 100 ns /cs to end of write t cw 55 70 80 ns /lb, /ub to end of write t bw 55 70 80 ns address valid to end of write t aw 55 70 80 ns address setup time t as 0 0 0 ns write pulse width t wp 50 55 60 ns write recovery time t wr 0 0 0 ns data valid to end of write t dw 30 35 40 ns data hold time t dh 0 0 0 ns /we to output in high impedance t whz 25 30 35 ns note output active from end of write t ow 5 5 5 ns note the output load is 1ttl + 5 pf.
data sheet m14670ej7v 1 ds 13 pd442002-x write cycle timing chart 1 (/we controlled) t wc t cw t bw t whz t dw t dh t ow indefinite data out high-z high-z data in indefinite data out address (input) /cs (input) /lb, /ub (input) i/o (input / output) t aw t wp t as t wr /we (input) cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remarks 1. write operation is done during the overlap time of a low level /cs, a low level /we and a low level /lb (or low level /ub). 2. if /cs changes to low level at the same time or after the change of /we to low level, the i/o pins will remain high impedance state. 3. when /we is at low level, the i/o pins are always high impedance. when /we is at high level, read operation is executed. therefore /oe should be at high level to make the i/o pins high impedance.
data sheet m14670ej7v 1 ds 14 pd442002-x write cycle timing chart 2 (/cs controlled) t wc t as t cw t dw t dh data in high-z address (input) /cs (input) /lb, /ub (input) i/o (input) high-z t aw t wp t wr /we (input) t bw cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /cs, a low level /we and a low level /lb (or low level /ub).
data sheet m14670ej7v 1 ds 15 pd442002-x write cycle timing chart 3 (/lb, /ub controlled) t wc t dw t dh data in high-z address (input) /lb, /ub (input) i/o (input) high-z t aw t wp t wr /we (input) t as t bw /cs (input) t cw cautions 1. during address transition, at least one of pins /cs, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during the overlap time of a low level /cs, a low level /we and a low level /lb (or low level /ub).
data sheet m14670ej7v 1 ds 16 pd442002-x low v cc data retention characteristics (t a = ?25 to +85 c) parameter symbol test condition -bb70x -bc70x -dd85x, -dd10x unit min. typ. max. min. typ. max. min. typ. max. data retention v ccdr1 /cs v cc ? 0.2 v 1.0 3.6 1.0 3.6 1.0 2.2 v supply voltage v ccdr2 /lb = /ub v cc ? 0.2 v, 1.0 3.6 1.0 3.6 1.0 2.2 /cs 0.2 v data retention i ccdr1 v cc = 1.2 v, /cs v cc ? 0.2 v 0.15 2 0.15 2 0.15 2 a supply current i ccdr2 v cc = 1.2 v, 0.15 2 0.15 2 0.15 2 /lb = /ub v cc ? 0.2 v, /cs 0.2 v chip deselection t cdr 0 0 0 ns to data retention mode operation t r t rc note t rc note t rc note ns recovery time note t rc : read cycle time
data sheet m14670ej7v 1 ds 17 pd442002-x data retention timing chart (1) /cs controlled v ih (min.) v ccdr (min.) v il (max.) /cs /cs v cc ? 0.2 v gnd v cc (min.) note t cdr data retention mode t r v cc note 2.7 v (-bb70x), 2.2 v (-bc70x), 1.8 v (-dd85x, -dd10x) remark on the data retention mode by controlling /cs, the other pins (address, i/o, /we, /oe, /lb, /ub) can be in high impedance state. (2) /lb, /ub controlled t cdr data retention mode v ih (min.) v ccdr (min.) v il (max.) t r /lb, /ub /lb, /ub v cc ? 0.2 v gnd v cc v cc (min.) note note 2.7 v (-bb70x), 2.2 v (-bc70x), 1.8 v (-dd85x, -dd10x) remark on the data retention mode by controlling /lb and /ub, the input level of /cs must be v cc ? 0.2 v or 0.2 v. the other pins (address, i/o, /we, /oe) can be in high impedance state.
data sheet m14670ej7v 1 ds 18 pd442002-x package drawing s wb s wa 6 5 4 3 2 1 a b abcdefgh sy sy1 m sb x ab s 48-pin tape fbga (8x6) item millimeters d e 8.0 0.1 6.0 0.1 w a 0.2 0.94 0.10 b x 0.08 y 0.1 e 0.75 a1 0.24 0.05 a2 0.70 0.40 0.05 index mark index mark a a2 a1 ze zd y1 0.2 zd 1.125 ze 1.375 p48f9-75-bc2 e e d
data sheet m14670ej7v 1 ds 19 pd442002-x recommended soldering conditions please consult with our sales offices for soldering conditions of the pd442002-x. types of surface mount device pd442002f9-bc2-a note : 48-pin tape fbga (8x6) note lead-free product
data sheet m14670ej7v 1 ds 20 pd442002-x revision history edition/ page type of location description date previous this revision (previous edition this edition) edition edition 7th edition/ throughout throughout deletion class -bb55x, -bb85x, -bc85x, -bc10x, -dd12x dec. 2003 p.2, 21 p.2, 19 modification package code f9-bc1 f9-bc2-a addition "note lead-free product" has been added. p.2 p.2 modification marking image lead-free mark has been added. index mark has been modified. p.20 p.18 modification package drawing package drawing has been changed
data sheet m14670ej7v 1 ds 21 pd442002-x [ memo ]
data sheet m14670ej7v 1 ds 22 pd442002-x [ memo ]
data sheet m14670ej7v1ds 23 pd442002-x 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. notes for cmos devices
pd442002-x the information in this document is current as of ju l y, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ?

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